The present invention relates generally to integrated circuits, and more particularly, to an improved design of a dual-voltage three-state buffer circuit using a tri-state level shifter.
A conventional dual-voltage three-state buffer includes two level shifters to control a post driver circuit that is made of PMOS and NMOS transistors. The two level shifters translate lower voltage signals to higher voltage signals. The post driver circuit determines the output of the overall circuit by deciding which transistor is to be turned on or off. However, the time it takes for the PMOS and NMOS transistors to turn on or off is different, since PMOS transistors are usually slower to drive than NMOS transistors. The time required for a signal to output from each of the level shifters may also be different, since different input signals can create different paths for the signals to travel through, wherein some paths may take more time than the others. With all these timing differences, a cross-bar current can occur during the switching of the transistors in the post driver circuit, thereby degrading the performance for the circuit. In order for a conventional dual-voltage three-state buffer to solve such issues, unbalanced inverters are inserted between the level shifter outputs and the transistors of the post driver circuit. While this method reduces the cross-bar current of the post driver circuit, the inverters are extremely unbalanced, consume extra power, and require additional layout areas.
Desirable in the art of dual-voltage buffer designs are designs that provide less power consumption, smaller layout area, and better versatility.